Optimal Vlsi Architectural Synthesis Area, Performance and Testability

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dc.contributor.authorAllen, Jonathan
dc.date.accessioned2019-02-22T07:59:09Z
dc.date.accessioned2024-06-27T15:51:39Z
dc.date.available2019-02-22T07:59:09Z
dc.date.available2024-06-27T15:51:39Z
dc.date.issued1992
dc.identifier.isbn978-1-4615-4018-2
dc.identifier.urihttps://drs.ess.gov.et/handle/123456789/46768
dc.language.isoenen_US
dc.publisherSpringer Science+Business Media New Yorken_US
dc.subjectArea, Performance and Testabilityen_US
dc.titleOptimal Vlsi Architectural Synthesis Area, Performance and Testabilityen_US
dc.typeBooken_US

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