Verilog Coding for Logic Synthesis
| dc.contributor.author | Fook Lee, Weng | |
| dc.date.accessioned | 2019-07-30T09:55:35Z | |
| dc.date.accessioned | 2024-04-26T12:49:06Z | |
| dc.date.available | 2019-07-30T09:55:35Z | |
| dc.date.available | 2024-04-26T12:49:06Z | |
| dc.date.issued | 2003 | |
| dc.identifier.uri | https://drs.ess.gov.et/handle/12345678/77320 | |
| dc.language.iso | en | en_US |
| dc.publisher | John Wiley & Sons, Inc | en_US |
| dc.subject | Verilog Coding for Logic Synthesis | en_US |
| dc.title | Verilog Coding for Logic Synthesis | en_US |
| dc.type | Book | en_US |